Semiconductor memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJenn-Gwo Hwu, Samuel C. Pan, Chien-Shun Liao, Kuan-Hao Tseng
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Abstract
A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10−4 Ωcm to 1.0×104 Ωcm or a sheet resistance in a range from 1.0×102Ω/□ to 1.0×1010Ω/□.
Claims10
A semiconductor memory device comprising:
- a transistor having a gate, a source and a drain;
- and
- a metal-insulator-semiconductor (MIS) structure, wherein:
- the transistor and the MIS structure are disposed on a common substrate,
- the MIS structure includes:
- a dielectric layer disposed on a semiconductor region;
- and
- an electrode disposed on the dielectric layer and coupled to the drain of the transistor,
- the electrode includes a bulk portion and a first portion, both disposed on the dielectric layer,
- the first portion has a higher resistance value or a higher sheet resistance than the bulk portion,
- the first portion has a resistance value in a range from 1.0×10−4 Ωcm to 1.0×104 Ωcm or a sheet resistance in a range from 1.0×102 Ω/□ to 1.0×1010 Ω/□, and
- the dielectric layer underlying the bulk portion and the first portion has a uniform thickness.
A semiconductor dynamic random access memory comprising a plurality of memory cells, a word line and a bit line, wherein:
- each of the memory cells includes:
- a transistor having a gate, a source and a drain;
- and
- a metal-insulator-semiconductor (MIS) structure,
- the MIS structure includes:
- a dielectric layer disposed on a semiconductor region;
- and
- an electrode disposed on the dielectric layer and coupled to the drain of the transistor,
- the electrode includes a bulk portion and a first portion, both disposed on the dielectric layer,
- the first portion has a higher resistance value or a higher sheet resistance than the bulk portion,
- the first portion has a resistance value in a range from 1.0×10−4 Ωcm to 1.0×104 Ωcm or a sheet resistance in a range from 1.0×102 Ω/□ to 1.0×1010 Ω/□, and
- the electrode is made of a metal selected from the group consisting of Al, Cu, Ni, W and Pt.
A semiconductor memory device comprising:
- a first transistor having a gate, a source and a drain;
- a second transistor having a gate, the source and a drain;
- and
- first and second metal-insulator-semiconductor (MIS) structures, wherein:
- the first and second transistors and the first and second MIS structures are disposed on a common substrate,
- each of the first and second MIS structures includes:
- a dielectric layer disposed on a semiconductor region;
- and
- an electrode disposed on the dielectric layer and coupled to the drain of the transistor,
- the electrode includes a bulk portion and a first portion, both disposed on the dielectric layer,
- the bulk portion and the first portion are made of a same conductive material,
- a thickness of the first portion is smaller than a thickness of the bulk portion,
- the bulk portion of the first and second MIS structures is coupled to the drain of the first and second transistors, respectively, and
- the first transistor and the second transistor shares the source.
Dependencies are inferred from the claim text.