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US 10,381,350 B2Granted
Floating body memory cell having gates favoring different conductivity type regions
AssigneeIntel Corporation
InventorsPeter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
Life of this patent
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Abstract
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
Claims20
An integrated circuit structure, comprising:
- a substrate comprising silicon, the substrate having a P well region having a first fin protruding therefrom, and the substrate having an N well region having a second fin and a third fin protruding therefrom, wherein the P well region is adjacent to the N well region in the substrate;
- a trench isolation structure on the substrate between a lower portion of the first fin and a lower portion of the second fin;
- a gate dielectric layer over an upper portion of the first fin, the gate dielectric layer over an upper portion of the second fin, the gate dielectric layer over an upper portion of the third fin, and the gate dielectric layer on the trench isolation structure, wherein the gate dielectric layer is continuous between the first and second fins and is continuous between the second and third fins, and wherein the gate dielectric layer comprises hafnium and oxygen;
- a first gate layer over the gate dielectric layer over the second fin and over the third fin but not over the first fin, wherein the first gate layer is further over a portion of but not all of the trench isolation structure, and wherein the first gate layer comprises titanium and nitrogen;
- and
- a second gate layer over the first fin, wherein the second gate layer is further over the trench isolation structure and over the first gate layer, wherein the second gate layer comprises titanium.
3 more elements
An integrated circuit structure, comprising:
- a substrate comprising silicon, the substrate having a first fin, a second fin and a third fin protruding therefrom;
- a trench isolation structure on the substrate between a lower portion of the first fin and a lower portion of the second fin;
- a gate dielectric layer over an upper portion of the first fin, the gate dielectric layer over an upper portion of the second fin, the gate dielectric layer over an upper portion of the third fin, and the gate dielectric layer on the trench isolation structure, wherein the gate dielectric layer is continuous between the first and second fins and is continuous between the second and third fins, and wherein the gate dielectric layer comprises hafnium and oxygen;
- a first gate layer over the gate dielectric layer over the second fin and over the third fin but not over the first fin, wherein the first gate layer is further over a portion of but not all of the trench isolation structure, and wherein the first gate layer comprises titanium and nitrogen;
- and
- a second gate layer over the first fin, wherein the second gate layer is further over the trench isolation structure and over the first gate layer, wherein the second gate layer comprises titanium.
3 more elements
Dependencies are inferred from the claim text.