Structure and method for equal substrate to channel height between N and P fin-FETs

A fin field effect transistor (fin-FET) device comprising:

• a substrate layer;
• a plurality of N-type areas, each N-type area made of N-type material and located above the substrate layer;
• a plurality of P-type areas, each P-type area made of P-type material and located above the substrate layer and adjacent to at least one N-type area of the plurality of N-type areas;
• a plurality of filled cavities, at least one filled cavity positioned horizontally between a P-type area of the plurality of P-type areas and an adjacent N-type area of the plurality of N-type areas such that a top surface of the P-type area, a top surface of the adjacent N-type area and a top surface of the at least one filled cavity are coplanar and each filled cavity of the plurality of filled cavities extends vertically into the substrate layer;
• and
• a plurality of intersections, each intersection formed along the substrate layer between a P-type area of the plurality of P-type areas and a filled cavity of the plurality of filled cavities or between an N-type area of the plurality of N-type areas and a filled cavity of the plurality of filled cavities, each intersection forming a right angle at a cross-section of the substrate layer, and each intersection having no corner rounding;
• wherein each P-type area of the plurality of P-type areas and each N-type area of the plurality of N-type areas have an equal channel height, an equal substrate to channel interface and a minimum pre-defined isolation spacing for a N to P channel boundary between N and P active regions in a direction parallel to the substrate layer, the minimum pre-defined isolation spacing dependent upon the N-type material and the P-type material.