Logic gate designs for 3D monolithic direct stacked VTFET
AssigneeInternational Business Machines Corporation
InventorsChen Zhang, Tenko Yamashita, Terence B. Hook
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Abstract
Logic gate designs (e.g., NAND, NOR, Inverter) for stacked VTFET designs are provided. In one aspect, a logic gate device is provided. The logic gate device includes: at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2); a power rail connected to a power contact of the logic gate device; and a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device. A method of forming a logic gate device is also provided.
Claims10
A method of forming a logic gate device, the method comprising the steps of:
- patterning at least one first fin and at least one second fin in a wafer;
- forming a device stack alongside the first fin and the second fin, wherein the device stack comprises a first top VTFET (VTFET1A) and a first bottom VTFET (VTFET2A) that share the first fin, and a second top VTFET (VTFET1B) and a second bottom VTFET (VTFET2B) that share the second fin, and wherein the device stack further comprises a sacrificial layer;
- patterning the sacrificial layer to disconnect the sacrificial layer in between the first fin and the second fin;
- removing a first disconnected portion of the sacrificial layer and replacing the first disconnected portion of the sacrificial layer with contact metal to form a ground contact connected to top source and drains of the VTFET2A;
- and
- removing a second disconnected portion of the sacrificial layer and replacing the second disconnected portion of the sacrificial layer with the contact metal to form an output contact connected to top source and drains of the VTFET2B, wherein the ground contact and the output contact are disconnected from one another.
Dependencies are inferred from the claim text.