Semiconductor device including resistor structure

A semiconductor device comprising:

• a lower interlayer insulating layer configured to cover a plurality of gate structures and side walls of the plurality of gate structures, the plurality of gate structures being on a substrate, the substrate including a transistor area and a resistor area;
• a resistor structure including a resistor layer and an etch stop pattern sequentially stacked, in the resistor area, on the plurality of gate structures and the lower interlayer insulating layer;
• an upper interlayer insulating layer on the lower interlayer insulating layer so as to cover the resistor structure in the transistor area and the resistor area;
• contact structures including a resistor contact structure and a transistor contact structure, the resistor contact structure configured to pass through the upper interlayer insulating layer and the etch stop pattern and contact the resistor layer, and the transistor contact structure configured to pass through the upper interlayer insulating layer and the lower interlayer insulating layer and contact the substrate;
• a resistor contact spacer between the upper interlayer insulating layer, the etch stop pattern, and the resistor contact structure, the resistor contact spacer including a first resistor contact spacer and a second resistor contact spacer, the second resistor contact spacer being between the first resistor contact spacer and the resistor contact structure, a top end of the second resistor contact spacer being located at a lower level than a top end of the first resistor contact spacer;
• and
• a transistor contact spacer between the upper interlayer insulating layer, the etch stop pattern, and the transistor contact structure, the transistor contact spacer including a first transistor contact spacer and a second transistor contact spacer, the second transistor contact spacer being between the first transistor contact spacer and the transistor contact structure, a top end of the second transistor contact spacer being located at a lower level than a top end of the first transistor contact spacer.