US 10,381,343 B2 · Electrostatic protection device of LDMOS silicon controlled structure

Abstract

An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (310), an N-well (320) and a P-well (330) on the substrate, a gate electrode (340) overlapping on the P-well (330) and extending to an edge of the N-well (320), a first N+ structure and a first P+ structure provided in the N-well (320), and a second N+ structure and a second P+ structure provided in the P-well (330), the first N+ structure being a drain electrode N+ structure (322), the first N+ structure being a drain electrode N+ structure (322), the first P+ structure being a drain electrode P+ structure (324), the second N+ structure being a source electrode N+ structure (332), the second P+ structure being a source P+ structure (334), and a distance from the drain electrode P+ structure (324) to the gate electrode (340) being greater than a distance from the drain electrode N+ structure (322) to the gate electrode (340).

Claims20

Dependent claims

An electrostatic protection device of an LDMOS silicon controlled structure, comprising:

a P-type substrate;
an N-well and a P-well on the substrate;
a gate overlapping the P-well and extending to an edge of the N-well;
a first N+ structure and a first P+ structure provided in the N-well;
a second N+ structure and a second P+ structure provided in the P-well;
wherein the first N+ structure is a drain N+ structure, the first P+ structure is a drain P+ structure;
the second N+ structure is a source N+ structure, the second P+ structure is a source P+ structure;
a distance from the drain P+ structure to the gate is greater than a distance from the drain N+ structure to the gate.

5 more elements

An electrostatic protection device of an LDMOS silicon controlled structure, comprising:

a substrate;
a P-type epitaxial layer on the substrate;
an N-well and a P-well on the P-type epitaxial layer;
a gate overlapping the P-well and extending to an edge of the N-well;
a first N+ structure and a first P+ structure provided in the N-well;
a second N+ structure and a second P+ structure provided in the P-well;
wherein the first N+ structure is a drain N+ structure, the first P+ structure is a drain P+ structure;
the second N+ structure is a source N+ structure, the second P+ structure is a source P+ structure;
a distance from the drain P+ structure to the gate is greater than a distance from the drain N+ structure to the gate.

6 more elements

Dependencies are inferred from the claim text.

Electrostatic protection device of LDMOS silicon controlled structure

Life of this patent

Electrostatic protection device of LDMOS silicon controlled structure

Life of this patent

Abstract

Claims20