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US 10,381,339 B1Granted
Integrated circuits with memory cell test circuits and methods for producing the same
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsChenchen Jacob Wang, Teck Leong Wee, Dimitri Houssameddine
Life of this patent
Estimating the term…
Abstract
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first and second dummy memory cell positioned within a dummy memory bank area. A first dummy top electrode overlies the first and second dummy memory cells, and is in electrical communication with the first and second dummy memory cells. A test circuit is in electrical communication with the first dummy top electrode.
Claims18
An integrated circuit comprising:
- a dummy memory bank area;
- a first dummy memory cell positioned within the dummy memory bank area, wherein the first dummy memory cell comprises a fixed layer that is magnetic, a barrier layer that is non-magnetic, and a free layer that is magnetic;
- a second dummy memory cell positioned within the dummy memory bank area;
- a first dummy top electrode overlying the first dummy memory cell and the second dummy memory cell, wherein the first dummy top electrode is in electrical communication with the first dummy memory cell and the first dummy top electrode is in electrical communication with the second dummy memory cell;
- and
- a test circuit in electrical communication with the first dummy top electrode.
3 more elements
An integrated circuit comprising:
- a first dummy memory cell;
- a test circuit;
- a first dummy top electrode overlying the first dummy memory cell, where the first dummy top electrode is in electrical communication with the first dummy memory cell and with the test circuit;
- an active memory cell;
- an active top electrode overlying the active memory cell, wherein the active top electrode is in electrical communication with the active memory cell and wherein the active top electrode is electrically isolated from the test circuit;
- and
- wherein the active memory cell and the first dummy memory cell comprise a fixed layer that is magnetic, a barrier layer that is non-magnetic, and a free layer that is magnetic.
4 more elements
A method of producing an integrated circuit comprising:
- forming a first dummy memory cell within a dummy memory bank area, wherein the first dummy memory cell comprises a fixed layer that is magnetic, a barrier layer that is non-magnetic, and a free layer that is magnetic;
- forming a second dummy memory cell within the dummy memory bank area;
- forming a first dummy top electrode in electrical communication with both the first dummy memory cell and the second dummy memory cell, wherein the first dummy top electrode overlies both the first dummy memory cell and the second dummy memory cell;
- and
- forming a test circuit in electrical communication with the first dummy top electrode.
2 more elements
Dependencies are inferred from the claim text.