Packages with Si-substrate-free interposer and method forming same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen
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Abstract
A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.
Claims20
A package of integrated circuits, the package comprising:
- a plurality of dielectric layers;
- a plurality of redistribution lines in each of the plurality of dielectric layers;
- a through-dielectric via penetrating through the plurality of dielectric layers, wherein the through-dielectric via has a substantially straight edge penetrating through the plurality of dielectric layers;
- stacked vias in the plurality of dielectric layers, wherein the stacked vias are electrically connected to each other to form a continuous electrical connection penetrating through the plurality of dielectric layers;
- a plurality of bond pads over and connected to the through-dielectric via and the stacked vias;
- a first dielectric layer, with the plurality of bond pads located in the first dielectric layer;
- and
- a first device die bonded to the first dielectric layer and a first portion of the plurality of bond pads.
A package of integrated circuits, the package comprising:
- a plurality of dielectric layers;
- stacked vias penetrating through the plurality of dielectric layers, wherein the stacked vias have dual damascene structures, and the stacked vias are interconnected to form a continuous electrical connection structure, with edges of upper ones of the stacked vias flush with edges of respective lower ones of the stacked vias;
- a first dielectric layer over and contacting the plurality of dielectric layers;
- a first bond pad in the first dielectric layer, wherein the first bond pad is in physical contact with a top surface of the stacked vias;
- a device die over the plurality of dielectric layers, wherein the device die is bonded to underlying structures through a bonding structure comprising:
- dielectric-to-dielectric bonding, with a surface dielectric layer of the device die bonded to the first dielectric layer through Si—O—Si bonds;
- and
- copper-to-copper bonding, with copper of the first bond pad bonded to and physically joined to copper of an additional bond pad in the device die;
- and
- a die stack over the device die.
A package of integrated circuits, the package comprising:
- a plurality of dielectric layers;
- a passive device in the plurality of dielectric layers;
- a through-dielectric via penetrating through the plurality of dielectric layers;
- stacked vias in the plurality of dielectric layers, wherein the stacked vias are electrically connected to each other to form a continuous electrical connection penetrating through the plurality of dielectric layers;
- a first bond pad over and contacting a top via in the stacked vias;
- a second bond pad over and contacting the through-dielectric via;
- and
- a device die over and bonded to both the first bond pad and the second bond pad.
Dependencies are inferred from the claim text.