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US 10,381,288 B2Granted
Packaged semiconductor die and CTE-engineering die pair
AssigneeIntel Corporation
InventorChuan Hu
Life of this patent
Estimating the term…
Abstract
Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.
Claims20
A semiconductor package, comprising:
- a molding layer;
- a semiconductor die in the molding layer, the semiconductor die having a surface area;
- and
- a CTE-engineering die in the molding layer, the CTE-engineering die bonded to the semiconductor die, the CTE-engineering die having a surface area the same and in alignment with the surface area of the semiconductor die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.
1 more element
A semiconductor package, comprising:
- a substrate comprising a core material and one or more build-up-layers on the core material;
- a semiconductor die in the core material, the semiconductor die having a surface area;
- and
- a CTE-engineering die in the core material, the CTE-engineering die bonded to the semiconductor die, the CTE-engineering die having a surface area the same and in alignment with the surface area of the semiconductor die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.
1 more element
An apparatus, comprising:
- a bumpless build-up layer (BBUL) package comprising a first build-up layer and a second build-up layer;
- a semiconductor die in the first build-up layer of the BBUL package, the semiconductor die having a surface area;
- and
- a CTE-engineering die in the first build-up layer of the BBUL package, the CTE-engineering die bonded to the first semiconductor die, the CTE-engineering die having a surface area the same and in alignment with the surface area of the first semiconductor die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the first semiconductor die, wherein the CTE-engineering die comprises a metal, wherein the CTE-engineering die has a CTE different than a CTE of the first semiconductor die;
- and
- a second semiconductor die housed in the second build-up layer of the BBUL package.
3 more elements
Dependencies are inferred from the claim text.