Control unit and electric power steering device

A control unit controlling a motor in an electronic power steering device, comprising:

• a heat dissipation substrate including
• an electronic component including a semiconductor die of a field effect transistor and a heat spreader that is joined to a lower surface of the semiconductor die, and
• a plurality of thermal vias which pass through a mounting surface on which the heat spreader is mounted, a rear surface of the mounting surface, and the heat dissipation substrate between the mounting surface and the rear surface;
• and
• a heat sink provided on a rear surface side of the mounting surface and conducting heat of the heat dissipation substrate at least on a rear surface of the heat spreader through a thermal interface material;
• wherein in the heat dissipation substrate,
• at least the plurality of thermal vias are disposed in a projection region of the heat spreader in which the heat spreader is projected to the mounting surface in a direction perpendicular to the mounting surface,
• the plurality of thermal vias include a metal thin film on an inner wall of a through-hole passing through the heat dissipation substrate between the mounting surface and a rear surface of the mounting surface,
• a surface density of the plurality of thermal vias which occupy the mounting surface per unit area is at least partially different,
• the plurality of thermal vias do not exist on an outer side of the projection region of the heat spreader,
• the plurality of thermal vias surrounding a periphery of the semiconductor die are disposed in a vicinity of an outer edge of the heat spreader, the plurality of thermal vias being disposed on an outer side in a projection region of the semiconductor die and in the projection region of the heat spreader,
• the plurality of thermal vias include:
• a first thermal via located in the vicinity of the outer edge or the heat spreader;
• a second thermal via located inside the projection region of the semiconductor die and adjacent to the first thermal via, and a third thermal via located on an inner side of the projection region of the semiconductor die more than the adjacent second thermal via is located, and
• an arrangement interval between the first thermal via and the second thermal via is larger than an arrangement interval between the third thermal via and the adjacent second thermal via.