Vertically stacked multi-channel transistor structure
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Tenko Yamashita, Chun-Chen Yeh, Ruilong Xie
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Abstract
A substrate structure for a vertically stacked transistor includes a substrate having at least one fin and a cavity formed through a portion of the substrate. An inner spacer disposed in the cavity. A first epitaxy layer disposed upon the substrate, and a liner is disposed on portions of the first epitaxy layer and the inner spacer. A second epitaxy layer is disposed upon a top portion of the liner. The first epitaxy layer and the second epitaxy layer share a common U-shaped fin body formed by the inner spacer and the at least one fin.
Claims14
A method of fabricating a vertically stacked transistor, comprising:
- receiving a substrate structure having a substrate and a hard mask formed on a top surface of the substrate;
- forming a first recess within a portion of the substrate and the hard mask;
- forming a sacrificial layer within the first recess;
- forming a substrate layer upon a top surface of the sacrificial layer;
- forming at least one fin in the substrate;
- forming at least one second recess extending through portions of the substrate layer, the sacrificial layer, and the substrate;
- removing at least a portion of the sacrificial layer within the at least one second recess to form a cavity;
- forming an inner spacer in the cavity;
- forming a first epitaxy layer upon the substrate;
- forming a liner on portions of the first epitaxy layer and the inner spacer;
- and
- forming a second epitaxy layer upon a top portion of the liner, the first epitaxy layer and the second epitaxy layer sharing a common U-shaped fin body formed by the inner spacer and the at least one fin.
Dependencies are inferred from the claim text.