Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same

A CMOS circuit, comprising:

• a partial gate-all-around (GAA) nFET;
• and
• a partial GAA pFET, wherein the partial GAA nFET and the partial GAA pFET each comprise:
• a fin comprising a stack of nanowire-like channel regions, the stack comprising at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region;
• a dielectric separation region comprising a dielectric material between the first and second nanowire-like channel regions, the dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region;
• a source electrode and a drain electrode on opposite sides of the fin;
• and
• a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions, the gate stack comprising a gate dielectric layer and a metal layer on the gate dielectric layer,
• wherein the metal layer of the gate stack does not extend between the first and second nanowire-like channel regions, and
• wherein an nFET channel height of each of the first and second nanowire-like channel regions of the partial GAA nFET is different than a pFET channel height of each of the first and second nanowire-like channel regions of the partial GAA pFET.

A method of forming a field effect transistor for an nFET and/or pFET device, the method comprising:

• forming a stack of alternating sacrificial layers and conducting channel layers on a substrate;
• etching the stack to form at least one fin, the at least one fin comprising a stack of nanowire-like channel regions, the stack comprising at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region;
• forming a source electrode on a first side of the at least one fin;
• and
• forming a drain electrode on a second side of the at least one fin opposite to the first side;
• removing the sacrificial layers of the stack;
• forming a dielectric separation region comprising a dielectric material along sidewalls of the first and second nanowire-like channel regions and between the first and second nanowire-like channel regions of the stack of nanowire-like channel regions, the dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region;
• removing portions of the dielectric separation region along the sidewalls of the first and second nanowire-like channel regions;
• and
• forming a gate stack comprising a gate dielectric layer and a metal layer on the gate dielectric layer,
• wherein the gate dielectric layer of the gate stack extends along a pair of sidewalls of the stack of nanowire-like channel regions,
• wherein the metal layer of the gate stack does not extend between the first and second nanowire-like channel regions of the stack of nanowire-like channel regions, and
• wherein the dielectric material of the dielectric separation region is different than a dielectric material of the gate dielectric layer.