PNP-type bipolar transistor manufacturing method
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorsPascal Chevalier, Gregory Avenier
Life of this patent
Estimating the term…
Loading patent…
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorsPascal Chevalier, Gregory Avenier
Estimating the term…
A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.
An integrated circuit PNP-type bipolar transistor, comprising:
An integrated circuit NPN-type bipolar transistor, comprising:
An integrated circuit NPN-type bipolar transistor, comprising:
Dependencies are inferred from the claim text.