Fan-out wafer level chip package structure

A package structure adapted to a voltage convertor circuit, comprising:

• a conductive frame including a bottom portion and a first partition plate to form a first accommodating region and a second accommodating region, wherein the first partition plate is located between the first accommodating region and the second accommodating region, and the bottom portion is divided into a first conductive portion and a second conductive portion insulated from the first conductive portion, and the first partition plate is electrically connected to the second conductive portion;
• a first power transistor packaged in the first accommodating region, wherein a drain of the first power transistor is electrically connected to the first conductive portion;
• a second power transistor packaged in the second accommodating region, wherein a drain of the second power transistor is electrically connected to the second conductive portion;
• a wiring layer electrically connected between a first active surface of the first power transistor and a second active surface of the second power transistor, wherein the wiring layer includes a high-side gate pad, a low-side gate pad, a switch contact pad, and at least one ground pad, the high-side gate pad is electrically connected to a gate of the first power transistor, the low-side gate pad is electrically connected to a gate of the second power transistor, and the switch contact pad is electrically connected to the source of the first power transistor and the drain of the second power transistor through the conductive frame;
• and
• a chip packaged in the second accommodating region together with the second power transistor and electrically connected to the first power transistor and the second power transistor by the conductive frame and the wiring layer,
• wherein an ending surface of the first partition plate, a first active surface of the first power transistor and a second active surface of the second power transistor are coplanar, and a source of the first power transistor is electrically connected to the drain of the second power transistor through the first partition plate and the second conductive portion.