Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap

A vertical transport fin field effect transistor with a self-aligned dielectric separator, comprising:

• a bottom source/drain region on a substrate;
• at least two vertical fins on the bottom source/drain region;
• an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins;
• an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and the insulating plug extends above the top surface of the bottom source/drain region to form an insulating cap;
• a gate dielectric layer on the sidewalls of two adjacent vertical fins of the at least two vertical fins and at least a portion of the sidewalls of the insulating cap;
• and
• the dielectric separator on the insulating plug.

A vertical transport fin field effect transistor with a self-aligned dielectric separator, comprising:

• a bottom source/drain region on a substrate;
• at least two vertical fins on the bottom source/drain region;
• an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins;
• an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and the insulating plug extends above the top surface of the bottom source/drain region to form an insulating cap, wherein the insulating cap does not extend laterally along the top surface of the bottom source/drain region;
• the dielectric separator on the insulating plug, wherein the dielectric separator has a width in the range of about 5 nm to about 40 nm;
• and
• a gate dielectric layer on the sidewalls of two adjacent vertical fins of the at least two vertical fins and at least a portion of the sidewalls of the insulating cap.