Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

A method of preparing a semiconductor-on-insulator device, the method comprising:

• forming a charge trapping multilayer on a front surface of a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a bulk region between the front and back surfaces, and a central plane of the single crystal semiconductor handle substrate between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of 100 Ohm-cm and further wherein the charge trapping multilayer comprises two or more passivated semiconductor layers, wherein each of the two or more passivated semiconductor layers comprises a semiconductor layer comprising a polycrystalline structure or an amorphous structure and comprising a material selected from the group consisting of silicon, SiGe, SiC, and Ge, and each of the two or more passivated semiconductor layers comprises a passivation layer comprising a semiconductor nitride or a semiconductor oxide, wherein a thickness of each of the two or more passivated semiconductor layers is between about 20 nanometers and about 1000 nanometers thick, and the charge trapping multilayer has a resistivity greater than about 1000 Ohm-cm;
• forming a semiconductor oxide layer on the charge trapping multilayer, wherein the semiconductor oxide layer has a thickness of at least about 0.1 micrometers;
• and
• bonding the semiconductor oxide layer to a dielectric layer on a front surface of a single crystal semiconductor donor substrate to thereby prepare a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor donor substrate and the other of which is a back surface of the single crystal semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor donor substrate, and a central plane of the single crystal semiconductor donor substrate between the front and back surfaces of the single crystal semiconductor donor substrate, wherein the single crystal semiconductor donor substrate comprises a cleave plane and the dielectric layer on the front surface of the single crystal semiconductor donor substrate.