Apparatuses and methods for latching redundancy repair addresses to avoid address bits overwritten at a repair block

An apparatus, comprising:

• a block of memory including primary memory and a plurality of redundant memory units;
• and
• a repair logic including a plurality of repair blocks, wherein a repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches, wherein the repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirect the memory access request to a redundant memory unit associated with the repair block;
• wherein the repair logic further comprises:
• an input circuit configured to serially receive each bit of the set of repair address bits and to shift each bit of the set of repair address bits into a respective input circuit latch response to a clock signal;
• a preload circuit configured to, in response to a load address signal, stage the set of repair address bits for a determination as to whether the set of repair address bits has been previously latched at one of the plurality of repair blocks;
• and
• a check repair circuit configured to couple the set of repair address bits to external address input lines in response to a check repair signal.

An apparatus, comprising:

• a block of memory including primary memory and redundant memory;
• and
• repair logic including a plurality of repair blocks coupled together sequentially in a pipeline, the repair logic configured to activate for latching a repair address in response to receipt of a set token signal, wherein, while activated, the repair logic further configured to sequentially provide a repair address mapped to a redundant memory unit of the redundant memory;
• wherein a first repair block and a second repair block are consecutive repair blocks in the pipeline and are configured to:
• allow or disallow the repair address to flow from the first repair block to the second repair block responsive at least in part, to an enable signal received from the second repair block.