Test mode circuit for memory apparatus
AssigneeMicron Technology, Inc.
InventorToru Ishikawa
Life of this patent
Estimating the term…
Abstract
Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number.
Claims20
An apparatus comprising:
- at least one memory cell array comprising a plurality of memory cells;
- and
- control circuit configured to receive read data from the plurality of memory cells and to compare the read data with reference data, wherein the control circuit comprises:
- a first comparison circuit configured to receive reference data and to provide a first error signal associated with a first number of bit errors based on a comparison of the reference data to the read data;
- and
- a second comparison circuit configured to receive the first error signal and to provide a second error signal associated with a second number of bit errors greater than the first number of bit errors.
An apparatus comprising:
- at least one memory cell array comprising a plurality of memory cells;
- and
- a control circuit configured to receive read data from the plurality of memory cells, configured to compare the read data with reference data, and further configured to suppress an error signal when a number of bit errors is less than an integer number of errors, wherein the control circuit comprises:
- a first comparison circuit configured to provide an intermediate error signal based on the number of bit errors being equal to or less than the integer number of errors, and
- a second comparison circuit configured to receive the first intermediate error signal and to provide a second error signal based on the first intermediate error signal.
An apparatus comprising:
- a memory array comprising a plurality of memory cells;
- and
- a control circuit configured to provide a plurality of first signals responsive to a plurality of bits of read data retrieved from the memory array, each of the plurality of first signals being configured to set to a first logic level when an error occurs in an associated one of the plurality of bits of read data and to a second logic level when no error occurs in an associated one of the plurality of bits of read data, the control circuit further configured to provide a second signal, the second signal being configured to set to a first state when a number of the first signals each setting to the first logic level is equal to or greater than a first number and to a second state when a number of the first signals each setting to the first logic level is smaller than the first number;
- wherein the first number is two or more.
Dependencies are inferred from the claim text.