Memory interface latch with integrated write-through and fence functions

A memory interface latch within an integrated circuit (IC) that includes a memory array, the memory interface latch configured to drive, to a data complement (Q_N) output coupled to a processor circuit, through a data path that includes one gate delay, the complement of a data signal received from an active bitline of the memory array, the memory interface latch comprising:

• a logic circuit having a first input coupled to the active bitline of the memory array and an output coupled to the Q_N output;
• and
• a feedback circuit coupled to a second input of the logic circuit through a feedback node, the feedback circuit further coupled to the output of the logic circuit at the Q_N output, the feedback circuit configured to, in response to receiving an asserted FENCE input signal, drive the feedback node to fixed logic value.

A design structure embodied on a non-transitory computer-readable storage medium readable by a machine used in design, manufacture, and simulation of an integrated circuit (IC) that includes a memory array and a memory interface latch, the design structure comprising elements that, when processed in a semiconductor manufacturing facility, produce an IC comprising:

• a logic circuit having a first input coupled to an active bitline of the memory array and an output coupled to an Q_N output;
• and
• a feedback circuit coupled to a second input of the logic circuit through a feedback node, the feedback circuit further coupled to the output of the logic circuit at the Q_N output, the feedback circuit configured to, in response to receiving an asserted FENCE input signal, drive the feedback node to fixed logic value.