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US 10,381,095 B1Granted
Non-volatile memory with smart erase verify
AssigneeSanDisk Technologies LLC
InventorsKei Date, Hideto Tomiie
Life of this patent
Estimating the term…
Abstract
In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.
Claims20
An apparatus, comprising:
- a plurality of non-volatile memory cells including a group of connected memory cells, the group of connected memory cells is a block of memory cells sharing a common set of word lines across the block, the block of memory cells includes multiple sub-block of memory cells, each sub-block of the multiple sub-blocks has its own set of one or more selection lines with respect to other sub-blocks of the block of memory cells;
- an erase circuit connected to the memory cells and configured to erase the group of connected memory cells by applying an erase signal to the group of connected memory cells;
- and
- an erase speed circuit configured to adjust an erase speed for a subset of the group of connected memory cells by adjusting voltages on the selection lines.
1 more element
A system, comprising:
- a plurality of non-volatile memory cells including a group of connected memory cells arranged in multiple sub-groups of connected memory cells, each sub-group of connected memory cells has its own set of one or more selection lines with respect to other sub-groups of connected memory cells;
- and
- peripheral circuits connected to the plurality of non-volatile memory cells and configured to apply a series of erase voltage bursts to the group of connected memory cells, separately erase verify each of the multiple sub-groups after a first erase voltage burst, characterize erase progress after the first erase voltage burst for each of the multiple sub-groups, adjust one or more voltages on the selection lines of the sub-groups based on the characterization of the erase verify to cause erase operations of the sub-groups to converge towards completing at a same time, and erase verify only a subset of the multiple sub-groups as a representative of all of the multiple sub-groups in response to the one or more additional erase voltage bursts.
A method of performing an erase process, the method comprising:
- applying an erase voltage pulse via a control line to multiple sub-blocks of a block of memory cells, the control line connected to the memory cells via selection gates having input signals;
- sensing information about erase speed for each of the multiple sub-blocks in response to the erase voltage pulse;
- applying one or more additional erase voltage pulses via the control line to the multiple sub-blocks;
- and
- adjusting an input signal for at least a subset of the selection gates based on the information about erase speed to cause erase speed for each of the multiple sub-blocks to converge in response to the one or more additional voltage pulses so that all of the sub-blocks will complete the erase process at a same time.
2 more elements
An apparatus, comprising:
- a plurality of non-volatile memory cells including a group of memory cells arranged in sub-groups of connected memory cells, each sub-group of connected memory cells is connected to a common control line and has its own select gate that connects to the common control line, each sub-group of connected memory cells has a separate selection line connected to its select gate;
- and
- means for erasing the memory cells by separately controlling an erase speed for the sub-groups of connected memory cells by adjusting one or more voltages on one or more of the separate selection lines in response to observing speed information for the sub-groups of connected memory cells during the erasing.
A non-volatile storage apparatus, comprising:
- a common bit line;
- a common set of word lines;
- a plurality of selection lines;
- a plurality of non-volatile memory cells arranged in multiple NAND strings connected to the common set of word lines and the plurality of selection lines, each of the NAND strings is connected to the common bit line, each NAND string of the multiple NAND strings has its own select gate that connects the common bit line to the respective NAND string, each NAND string of the multiple NAND strings has a separate selection line of the plurality of selection lines connected to its select gate;
- and
- a control circuit connected to the memory cells, the control circuit is configured to erase the memory cells by applying an erase signal to the memory cells and separately adjust an erase speed for a subset of the NAND strings by adjusting voltages on the selection lines.
3 more elements
Dependencies are inferred from the claim text.