3D memory with staged-level multibit programming

A memory device including a plurality of memory cells, comprising:

• a NAND string having 2N word lines, the NAND string having a first stack of cells C1(i) coupled with a first set of N word lines of the 2N word lines, and a second stack of cells C2(i) coupled with a second set of N word lines of the 2N word lines, where i is an index indicating a level of a cell in the first and second stacks, and i goes from 1 to N, and wherein level N is one of the uppermost level and the lowermost level in the first and second stacks;
• and
• a controller configured to program multiple bits of data per memory cell in the plurality of memory cells, including:
• logic to apply a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the plurality of memory cells in the first stack and then the second stack;
• and
• logic to select memory cells in the plurality of memory cells according to a programming order in which the final program stage S3 is applied to memory cells in the first stack and then the second stack at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i−1) of both the first and second stacks, and for at least one level (i) in the plurality of levels, the final program stage S3 is applied to level (i) of both the first and second stacks before the preliminary program stage Si is applied to level (i+3) of both the first and second stacks.