Nonvolatile memory device for suppressing read disturbances

A nonvolatile memory device comprising:

• a nonvolatile memory cell coupled between a bit line and a ground terminal and comprising a first PMOS transistor and a second PMOS transistor;
• a sensing circuit comprising a third PMOS transistor and a first NMOS transistor, wherein gates of the third PMOS transistor and the first NMOS transistor are coupled to the bit line, and drains of the third PMOS transistor and the first NMOS transistor are coupled to a sensing output line, and a source of the first NMOS transistor is coupled to the ground terminal;
• a first switching portion comprising a fourth PMOS transistor having a gate to which a first enable signal is applied, a source coupled to a supply voltage line, and a drain coupled to a source of the third PMOS transistor;
• a sensing output grounding portion comprising a second NMOS transistor having a gate to which a second enable signal is applied, a drain coupled to the sensing output line, and a drain coupled to the ground terminal;
• a resistive load/second switching portion comprising a fifth PMOS transistor having a gate to which a third enable signal is applied, a source coupled to the supply voltage line, and a drain coupled to the bit line;
• a bit line grounding portion comprising a third NMOS transistor having a gate to which a fourth enable signal is applied, a drain coupled to the bit line, and a source coupled to the ground terminal;
• and
• an enable signal generator receiving a sensing output signal from the sensing output line and a sense amplifier enable signal, and generating the first to fourth enable signals,
• wherein the enable signal generator configured to sequentially supply the first to fourth enable signal of high level if a sensing output signal of the sensing output line is changed from a high level into a low level.