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US 10,381,092 B2Granted
Semiconductor device
AssigneeToshiba Memory Corporation
InventorsShinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
Life of this patent
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Abstract
A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
Claims14
A semiconductor device comprising:
- an interface chip,
- a first memory chip including a first interconnect which extends from a back surface side to a top surface side of the first memory chip, the back surface side of the first memory chip and a top surface side of the interface chip facing with each other to establish an electrical connection between the first memory chip and the interface chip through the first interconnect;
- wherein the interface chip includes:
- a first FIFO receiving data from the first memory chip through the first interconnect;
- a second FIFO receiving the data from the first FIFO;
- and
- a pad outputting the data from the second FIFO, and
- wherein, in the interface chip, as viewed from above,
- the first FIFO is positioned closer to a center of the interface chip as compared with the pad, and
- the second FIFO is positioned closer to the pad rather than the first FIFO.
7 more elements
Dependencies are inferred from the claim text.