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US 10,381,091 B2Granted
Reduced voltage nonvolatile flash memory
AssigneeMicron Technology, Inc.
InventorKoji Sakui
Life of this patent
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Abstract
Systems include a first semiconductor die comprising a charge pump to generate power supply signals, a second semiconductor die comprising a memory array and programming circuitry, and a bus connected to the first and second semiconductor dies to carry the power supply signals to the programming circuitry. The programming circuitry is adapted to program memory cells of the memory array to respective threshold voltages that are each less than or equal to the first voltage.
Claims20
A system comprising:
- a first semiconductor die comprising a charge pump configured to receive a first voltage from an external power source and to generate power supply signals;
- a second semiconductor die comprising a memory array and programming circuitry;
- a bus connected to the first and second semiconductor dies to carry the power supply signals to the programming circuitry;
- and
- a microcontroller to read information from a selected memory cell of the memory array for a read operation by applying a gate voltage less than or equal to the first voltage to wordlines of one or more unselected memory cells of the memory array connected in series with the selected memory cell, wherein the microcontroller is adapted to program two or more bits of information in individual memory cells of the memory array;
- wherein the programming circuitry is adapted to program memory cells of the memory array to respective threshold voltages that are each less than or equal to the first voltage;
- wherein the programming circuitry is further adapted to program a selected memory cell of the memory array while applying gate voltages less than or equal to the first voltage to wordlines of each unselected memory cell of the memory array connected in series with the selected memory cell;
- and
- wherein the programming circuitry is further adapted to program the selected memory cell of the memory array while applying no voltage greater than the first voltage to each unselected memory cell of the memory array connected in series with the selected memory cell.
6 more elements
A system comprising:
- a first semiconductor die comprising a charge pump configured to receive a first voltage from an external power source and adapted to generate power supply signals;
- a second semiconductor die comprising a memory array and programming circuitry and configured to receive the first voltage from the external power source and to receive a power supply signal from the charge pump having a second voltage higher than the first voltage;
- a voltage regulator configured to receive a power supply signal from the charge pump having the second voltage and to provide a third voltage to the second semiconductor die;
- and
- a bus connected to the first and second semiconductor dies to carry the power supply signals to the programming circuitry;
- wherein the memory array comprises a plurality of memory cells arranged in a plurality of strings of memory cells with each string of memory cells of the plurality of strings of memory cells containing memory cells connected in series between a respective bitline and a sense amplifier;
- wherein the third voltage is lower than the second voltage and higher than the first voltage;
- wherein the programming circuitry is adapted to program the memory cells of the plurality of memory cells to respective threshold voltages that are each less than or equal to the first voltage;
- wherein the programming circuitry is further adapted to program a selected memory cell of the memory array while applying gate voltages less than or equal to the first voltage to wordlines of each unselected memory cell of the memory array connected in series with the selected memory cell;
- and
- wherein the programming circuitry is further adapted to program the selected memory cell of the memory array while applying no voltage greater than the first voltage to each unselected memory cell of the memory array connected in series with the selected memory cell.
8 more elements
A system comprising:
- a first semiconductor die comprising a charge pump configured to receive a first voltage from an external power source and to generate power supply signals;
- a second semiconductor die comprising a memory array and programming circuitry and configured to receive the first voltage, wherein the second semiconductor die is devoid of a charge pump, and wherein the first voltage is a lowest positive voltage for which the second semiconductor die is configured to receive;
- a bus connected to the first and second semiconductor dies to carry the power supply signals to the programming circuitry;
- and
- a microcontroller to read information from a selected memory cell of the memory array by applying a gate voltage less than or equal to the first voltage to wordlines of one or more unselected memory cells of the memory array connected in series with the selected memory cell, wherein the microcontroller is adapted to program two or more bits of information in individual memory cells of the memory array;
- wherein the programming circuitry is adapted to program memory cells of the memory array to respective threshold voltages that are each less than or equal to the first voltage;
- wherein the programming circuitry is further adapted to program a selected memory cell of the memory array while applying gate voltages less than or equal to the first voltage to wordlines of each unselected memory cell of the memory array connected in series with the selected memory cell;
- and
- wherein the programming circuitry is further adapted to program the selected memory cell of the memory array while applying no voltage greater than the first voltage to each unselected memory cell of the memory array connected in series with the selected memory cell.
6 more elements
Dependencies are inferred from the claim text.