System and method for generating random numbers based on non-volatile memory cell array entropy

A memory device, comprising:

• a plurality of pairs of memory cells, wherein each pair of the memory cells includes:
• first, second and third regions formed in a semiconductor substrate, wherein a first channel region of the substrate extends between the first and second regions, and a second channel region of the substrate extends between the second and third regions,
• a first floating gate disposed over and insulated from a first portion of the first channel region,
• a second floating gate disposed over and insulated from a first portion of the second channel region,
• a first select gate disposed over and insulated from a second portion of the first channel region, and
• a second select gate disposed over and insulated from a second portion of the second channel region;
• a controller configured to:
• apply one or more positive voltages to the second regions, or to the first and third regions, of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the first and second channel regions,
• measure the leakage currents, and
• generate a number based on the measured leakage currents.

A method of identifying a memory device that includes a plurality of memory cells, wherein each of the memory cells includes:

• first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions,
• a floating gate disposed over and insulated from a first portion of the channel region, and
• a select gate disposed over and insulated from a second portion of the channel region;
• the method comprising:
• applying one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions,
• measuring the leakage currents, and
• generating a number based on the measured leakage currents.

A method of identifying a memory device that includes a plurality of pairs of memory cells, wherein each pair of the memory cells includes:

• first, second and third regions formed in a semiconductor substrate, wherein a first channel region of the substrate extends between the first and second regions, and a second channel region of the substrate extends between the second and third regions,
• a first floating gate disposed over and insulated from a first portion of the first channel region,
• a second floating gate disposed over and insulated from a first portion of the second channel region,
• a first select gate disposed over and insulated from a second portion of the first channel region, and
• a second select gate disposed over and insulated from a second portion of the second channel region;
• the method comprising:
• applying one or more positive voltages to the second regions, or to the first and third regions, of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the first and second channel regions,
• measuring the leakage currents, and
• generating a number based on the measured leakage currents.