Erasing memory cells

A method of operating a memory device, comprising:

• applying a first voltage level to a source connected to a first end of a string of series-connected memory cells;
• applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells;
• and
• applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first voltage level to the source and applying the second voltage level to the data line;
• wherein a magnitude of the third voltage level is greater than a magnitude of the first voltage level and greater than a magnitude of the second voltage level;
• wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the third voltage level to the first access line, the first voltage level to the source and the second voltage level to the data line;
• and
• wherein applying the first voltage level to the source and applying the second voltage level to the data line comprises applying voltage levels that are each less than or equal to a select gate voltage applied during a sensing operation on the string of series-connected memory cells.

A method of operating a memory device, comprising:

• applying a first voltage level to a source connected to a first end of a string of series-connected memory cells;
• applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells;
• and
• applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first voltage level to the source and applying the second voltage level to the data line;
• wherein a magnitude of the third voltage level is greater than a magnitude of the first voltage level and greater than a magnitude of the second voltage level;
• wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the third voltage level to the first access line, the first voltage level to the source and the second voltage level to the data line;
• and
• wherein applying the first voltage level to the source and applying the second voltage level to the data line comprises applying voltage levels that are each less than or equal to a supply voltage Vcc of the memory device.

A method of operating a memory device, comprising:

• applying a first voltage level to a source connected to a first end of a string of series-connected memory cells;
• applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells;
• and
• applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first voltage level to the source and applying the second voltage level to the data line;
• applying a fourth voltage level to a second access line coupled to a second memory cell of the string of series-connected memory cells concurrently with applying the first voltage level to the source and applying the second voltage level to the data line;
• wherein a magnitude of the third voltage level is greater than a magnitude of the first voltage level and greater than a magnitude of the second voltage level;
• wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the third voltage level to the first access line, the first voltage level to the source and the second voltage level to the data line;
• wherein a magnitude of the fourth voltage level is less than the magnitude of the third voltage level;
• and
• wherein a polarity and the magnitude of the fourth voltage level are expected to decrease a threshold voltage of the second memory cell when concurrently applying the fourth voltage level to the second access line, the first voltage level to the source and the second voltage level to the data line.

A method of operating a memory device, comprising:

• applying a first voltage level to a source connected to a first end of a string of series-connected memory cells;
• applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells;
• applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first voltage level to the source and applying the second voltage level to the data line;
• wherein a magnitude of the third voltage level is greater than a magnitude of the first voltage level and greater than a magnitude of the second voltage level;
• and
• wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the third voltage level to the first access line, the first voltage level to the source and the second voltage level to the data line;
• determining whether the first memory cell is deemed to have a desired threshold voltage;
• if the first memory cell is not deemed to have the desired threshold voltage, increasing the magnitude of the third voltage level before repeating applying the first voltage level to the source, applying the second voltage level to the data line and applying the third voltage level to the first access line.

A method of operating a memory device, comprising:

• applying a first voltage level to a source connected to a first end of a string of series-connected memory cells;
• applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells;
• applying a third voltage level to a first plurality of access lines coupled to respective memory cells of a first plurality of memory cells of the string of series-connected memory cells concurrently with applying the first voltage level to the source and applying the second voltage level to the data line;
• applying a fourth voltage level to a second plurality of access lines coupled to respective memory cells of a second plurality of memory cells of the string of series-connected memory cells concurrently with applying the first voltage level to the source and applying the second voltage level to the data line;
• and
• applying a fifth voltage level to a third plurality of access lines coupled to respective memory cells of a third plurality of memory cells of the string of series-connected memory cells concurrently with applying the first voltage level to the source and applying the second voltage level to the data line;
• wherein a magnitude of the third voltage level is greater than a magnitude of the first voltage level and greater than a magnitude of the second voltage level;
• wherein a magnitude of the fourth voltage level is less than or equal to the magnitude of the third voltage level;
• wherein a magnitude of the fifth voltage level is less than or equal to the magnitude of the fourth voltage level;
• and
• wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the third voltage level to the first access line, the first voltage level to the source and the second voltage level to the data line.