Semiconductor memory device

A semiconductor memory device comprising:

• a memory string including a first transistor, a second transistor, and a plurality of memory cells provided along a first direction and between the first transistor and the second transistor, and stacked above a semiconductor substrate;
• a plurality of first word lines electrically connected to the memory string;
• a plurality of second word lines electrically connected to the memory string;
• a control unit configured to perform an erase operation that includes an erasing operation and a verifying operation, wherein the control unit:
• during the erasing operation, applies a first voltage to the first word lines, a second voltage, which is lower than the first voltage, to the second word lines, and an erasing voltage, which is higher than the first voltage, to one end of the memory string, and
• during the verifying operation, applies substantially the same voltage to the first word lines and the second word lines.