Bit line control that reduces select gate transistor disturb in erase operations

An apparatus, comprising:

• an erase circuit coupled to a memory string comprising a memory channel, wherein the erase circuit is configured to:
• decrease a voltage of a bit line at a drain end of the memory string from a reference voltage level to a negative voltage level;
• increase a voltage of a substrate at a source end of the memory string from a reference voltage level up to an intermediate voltage level in a first stage and increase the voltage of the substrate from the intermediate voltage level to an erase voltage threshold in a second stage to charge up the memory channel;
• and
• float the voltage of the bit line such that the floating voltage of the bit line couples up from the negative voltage level to the voltage of the substrate resulting in a potential gradient in an ungated channel region between the bit line and a select gate transistor at the drain end staying below the erase voltage threshold when the memory channel charges up to the erase voltage threshold.

A system comprising:

• a set of memory cells in a memory string, the memory string comprising a source end and a drain end, the source end connected to a substrate, the drain end connected to a bit line and a select gate transistor, and a channel including an ungated channel region extending between the select gate transistor and the bit line;
• and
• a control circuit coupled to the memory string to reduce a potential gradient in the ungated channel region during an erase operation, wherein the control circuit comprises:
• a first voltage supply circuit configured to step down a voltage of the bit line at the drain end from 0 V to a negative voltage level;
• a second voltage supply circuit configured to increase a voltage of the substrate at the source end from 0 V to an erase voltage threshold to charge up the channel;
• and
• a disconnect circuit configured to disconnect the bit line in relation to the increase in the voltage of the substrate delivered by the second voltage supply circuit, to float the voltage of the bit line and couple up the floating voltage of the bit line from the negative voltage level to the voltage of the substrate such that the potential gradient in the ungated channel region stays below the erase voltage threshold when the channel charges up to the erase voltage threshold.

A method comprising:

• at a first time, increasing a voltage of a substrate at a source end of a memory string from 0 V to an intermediate voltage level, and at a second time, increasing the voltage of the substrate from the intermediate voltage level to an erase voltage threshold;
• charging up a channel of the memory string to the erase voltage threshold for erasing memory cells based on increasing the voltage of the substrate, the memory string comprising the memory cells between the source end and a drain end, the drain end connected to a bit line and a drain of a select gate transistor, the source end connected to the substrate, and an ungated channel region extending between a contact of the bit line and the drain of the select gate transistor;
• driving a voltage of the bit line at 0 V;
• and
• at the second time, floating the voltage of the bit line from 0 V to couple the floating voltage of the bit line to the voltage of the substrate, the floating voltage rising to a first voltage level such that a voltage difference in the ungated channel region stays below the erase voltage threshold when the channel charges up.

An apparatus, comprising:

• a memory string comprising a set of memory cells and a memory channel between a source end and a drain end, the drain end connected to a select gate transistor and a bit line, and the source end connected to a substrate;
• means for driving a voltage of the bit line at the drain end;
• means for increasing a voltage of the substrate at the source end in one or more voltage steps to charge up the memory channel to an erase voltage threshold;
• and
• means for floating the voltage of the bit line in relation to increasing the voltage of the substrate to couple up the floating voltage of the bit line to the voltage of the substrate such that a potential gradient between the bit line and the select gate transistor in the memory channel stays below the erase voltage threshold when the memory channel charges up.