Three dimensional memory device with multiple stacked electrode layers

A memory device, comprising:

• a plurality of first electrode layers stacked in a first direction;
• a first semiconductor pillar extending in the first direction and piercing the first electrode layers;
• a plurality of second electrode layers stacked in the first direction
• a second semiconductor pillar extending in the first direction and piercing the second electrode layers;
• an interconnect provided between the first electrode layers and the second electrode layers in the first direction, a second electrode layer positioned at the bottom of the second electrode layers being stacked above a first electrode layer positioned at the top of the first electrode layers with the interconnect interposed, the interconnect being electrically connected to the first semiconductor pillar and the second semiconductor pillar;
• and
• a first connecting conductor connected to one of the first electrode layers and one of the second electrode layers, the first connecting conductor extending in the first direction, and crossing at least one of the second electrode layers.