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US 10,381,080 B2Granted
Apparatuses and methods for segmented SGS lines
AssigneeMicron Technology, Inc.
InventorsFeng Pan, Jaekwan Park, Ramin Ghodsi
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.
Claims16
An apparatus comprising:
- a first plurality of memory subblocks;
- a second plurality of memory subblocks;
- a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple one respective memory subblock of all of the first and second pluralities of memory subblocks to one signal line of a plurality of signal lines, wherein each first select gate control line of the plurality of first select gate control lines is configured to couple a single respective memory subblock to the one signal line;
- a second select gate control line configured to couple a source line to the first plurality of memory subblocks configured to be coupled to the one signal line;
- a third select gate control line different from the second select gate control line, the third select gate control line configured to couple the source line to the second plurality of memory subblocks configured to be coupled to the one signal line, and
- a plurality of access lines, each access line coupled to a memory cell in each memory subblock of the first and second pluralities of memory subblocks.
3 more elements
An apparatus comprising:
- a memory access line configured to access memory cells of a first plurality of memory subblocks and to access memory cells of a second plurality of memory subblocks;
- a plurality of select gate drain control lines, each select gate drain control line configured to selectively couple one respective memory subblock of the first and second pluralities of memory subblocks to one signal line of a plurality of signal lines, wherein each select gate drain control line is configured to couple a single respective memory subblock to the one signal line;
- a first select gate source control line configured to selectively couple a source line to the first plurality of memory subblocks configured to be coupled to the one signal line;
- and
- a second select gate source control line different from the first select gate source control line, the second select gate source control line configured to selectively couple the source line to the second plurality of memory subblocks configured to be coupled to the one signal line.
2 more elements
A method comprising:
- performing a program operation, wherein performing the program operation comprises:
- selectively activating first, second, and third select gate drain lines to couple a respective memory subblock of all of first, second, and third memory subblocks to one signal line of a plurality of signal lines;
- selectively deactivating a first select gate source line to decouple a source line from the first, second, and third memory subblocks configured to be coupled to the one signal line;
- and
- providing a voltage to a memory access line,
- wherein the memory access line is coupled to memory cells of the first, second, and third memory subblocks, and to memory cells of a fourth memory subblock configured to be coupled to the one signal line, and
- wherein the source line is decoupled from the fourth memory subblock configured to be coupled to the one signal line by a second select gate source line different from the first select gate source line, and the source line is not decoupled from the fourth memory subblock by the selectively deactivated first select gate source line.
4 more elements
Dependencies are inferred from the claim text.