Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors

An integrated circuit comprising:

• a pulse generator;
• and
• an array of two or more resistive processing units;
• wherein a given one of the resistive processing units comprises:
• an analog memory element coupled to a read row line and a read column line, the analog memory element configured to store a weight value as its conductance;
• a first current subtraction field-effect transistor (FET) coupled to the read row line and the analog memory element;
• and
• a second current subtraction FET coupled to the read column line and the analog memory element;
• wherein the pulse generator is configured:
• to receive a read pulse data stream;
• to generate a first voltage based on the read pulse data stream, the first voltage having a read pulse width based on the read pulse data stream;
• to generate a second voltage, the second voltage having a gate pulse width synchronized with the read pulse width of the first voltage;
• to apply the first voltage to one of the read row line and the read column line;
• and
• to apply the second voltage to a gate of one of the first current subtraction FET and the second current subtraction FET;
• wherein the second voltage reduces a measured conductance of the analog memory element to provide net current for the stored weight value.

A method for differential weight reading of an analog memory element in a resistive processing unit, comprising:

• receiving a read pulse data stream;
• generating a first voltage based on the read pulse data stream, the first voltage having a read pulse width based on the read pulse data stream;
• generating a second voltage, the second voltage having a gate pulse width synchronized with the read pulse width of the first voltage;
• applying the first voltage to one of a read row line and a read column line of the resistive processing unit;
• applying the second voltage to a gate of one of:
• a first current subtraction field-effect transistor (FET) coupled to the read row line and the analog memory element;
• and
• a second current subtraction FET coupled to the read column line and the analog memory element;
• and
• measuring a conductance of the analog memory element, wherein the measured conductance is reduced by application of the second voltage to said one of the first current subtraction FET and the second current subtraction FET to provide net current for a stored weight value of the analog memory element.