Multi-bit computing circuit for computing-in-memory applications and computing method thereof

A multi-bit computing circuit for computing-in-memory applications, which is controlled by a first bit line, a second bit line, a word line and a plurality of input ports, each of the input ports transmits an input value, and the multi-bit computing circuit for the computing-in-memory applications comprising:

• a memory cell array comprising a plurality of memory cells arranged in a matrix and connected to the first bit line, the second bit line, the word line and the input ports, wherein the memory cells store a plurality of weights which are formed in two's complement, and each of the memory cells generates a cell output signal according to one of the input values and one of the weights;
• and
• a capacitor sharing unit electrically connected to the memory cell array, and the capacitor sharing unit comprising:
• a plurality of switches electrically connected to the cell output signals, respectively;
• a plurality of capacitors electrically connected to the switches, respectively;
• and
• a sense amplifier electrically connected to the capacitors and generating a total operational value;
• wherein the capacitors are located among the switches and the sense amplifier, the switches are switched to generate a plurality of multiply results by the input values respectively multiplied by the weights, and then the total operational value is equal to a sum of the multiply results.