Ultra dense and stable 4T SRAM cell design having NFETs and PFETs
AssigneeInternational Business Machines Corporation
InventorsMyung-Hee Na, Robert Wong, Jens Haetty, Sean Burns
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Abstract
Ultra dense and stable 4T SRAM designs are provided. In one aspect, a 4T SRAM bitcell includes: two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to a word line, wherein a first one of the PFETs is connected to a first bit line via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, and wherein the PFETs are each separately connected to ground. An SRAM device including the present 4T SRAM bitcell as well as a method of operating the SRAM device are also provided.
Claims20
A 4 transistor (4T) static random access memory (SRAM) bitcell, comprising:
- two n-channel field-effect transistors (NFETs) cross-coupled with two p-channel FETs (PFETs), wherein the NFETs are both connected directly to a word line, wherein a first one of the PFETs is connected to a first bit line via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, wherein the PFETs are each separately connected to ground, and wherein cross-coupling between the NFETs and the PFETs comprises a first connection between only two devices which are the first PFET and the first NFET, and a second connection between only two other devices which are the second PFET and the second NFET.
A SRAM device, comprising:
- bit lines;
- word lines oriented orthogonal to the bit lines;
- bitcells at an intersection of the word lines and bit lines, wherein each bit cell comprises two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to one of the word lines, wherein a first one of the PFETs is connected to a first one of the bit lines via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, wherein the PFETs are each separately connected to ground, and wherein cross-coupling between the NFETs and the PFETs comprises a first connection between only two devices which are the first PFET and the first NFET, and a second connection between only two other devices which are the second PFET and the second NFET.
A method of operating a SRAM device, the method comprising the steps of:
- providing the SRAM device comprising:
- bit lines;
- word lines oriented orthogonal to the bit lines;
- bitcells at an intersection of the word lines and bit lines, wherein each bit cell comprises two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to a given one of the word lines, wherein a first one of the PFETs is connected to a first given one of the bit lines via a first one of the NFETs forming a zero (0) node of the 4T SRAM bitcell and a second given one of the PFETs is connected to a second bit line via a second one of the NFETs forming a one (1) node of the 4T SRAM bitcell, wherein the PFETs are each separately connected to ground, and wherein cross-coupling between the NFETs and the PFETs comprises a first connection between only two devices which are the first PFET and the first NFET, and a second connection between only two other devices which are the second PFET and the second NFET;
- passively retaining the zero (0) node using ground leak through the first PFET;
- and
- actively retaining the one (1) node using the second PFET.
Dependencies are inferred from the claim text.