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US 10,381,066 B2Granted
Semiconductor memory device with burst mode
AssigneeSK hynix Inc.
InventorsDaesuk Kim, Jaeil Kim
Life of this patent
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Abstract
A semiconductor device may include a data input and output circuit (I/O) configured to selectively or simultaneously drive input and output lines according to a burst length and a location of a memory area selected by an address to allow the semiconductor device to receive or output data regardless of the burst length being changed.
Claims24
A semiconductor device comprising:
- an input and output (I/O) control circuit configured to generate first and second write control signals selectively enabled and first to fourth write selection signals selectively enabled, according to a burst length signal and a selection address signal;
- and
- a data I/O circuit configured to transmit first transfer data loaded on a first I/O line to a first memory area and transmit second transfer data loaded on a second I/O line to a second memory area if a burst length determined by the burst length signal is set as a first burst length and configured to transmit the first transfer data to the first memory area or transmit the second transfer data to the second memory area if the burst length is set as a second burst length, based on the first to fourth write selection signals.
A semiconductor device comprising:
- an input and output (I/O) control circuit configured to generate first and second write control signals selectively enabled, first and second read control signals selectively enabled, first to fourth write selection signals selectively enabled, and first to fourth read selection signals selectively enabled, according to a burst length signal and a selection address signal during a write operation and a read operation;
- a write path circuit configured to latch data, configured to align the latched data based on the burst length signal and the first and second write control signals, and configured to output the aligned data as first transfer data and second transfer data through a first I/O line and a second I/O line;
- and
- a data I/O circuit configured to transmit the first transfer data loaded on the first I/O line to a first memory area and transmit the second transfer data loaded on the second I/O line to a second memory area if a burst length determined by the burst length signal is set as a first burst length and configured to transmit the first transfer data to the first memory area or transmit the second transfer data to the second memory area if the burst length is set as a second burst length, based on the first to fourth write selection signals.
1 more element
A semiconductor device comprising:
- a write path circuit configured to latch data, configured to align the latched data based on a burst length signal and first and second write control signals, and configured to output the aligned data as first transfer data and second transfer data through a first I/O line and a second I/O line;
- and
- a data input and output circuit (I/O) configured to selectively or simultaneously drive the first I/O line and the second I/O line according to a burst length and a location of a memory area selected by an address to allow the semiconductor device to receive or output data regardless of the burst length being changed.
Dependencies are inferred from the claim text.