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US 10,381,064 B1Granted
Apparatuses and methods for refreshing memory of a semiconductor device
AssigneeMicron Technology, Inc.
InventorMasaru Morohashi
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.
Claims13
An apparatus, comprising:
- a refresh counter circuit configured to provide a refresh address responsive a first active refresh command;
- a first latch circuit configured to latch the refresh address and provide a first latched refresh address;
- an address counter circuit configured to provide a count, wherein the count changes responsive to an oscillating signal;
- a redundancy circuit configured to receive the first latched refresh address and the count as a combined address, the redundancy circuit further configured to provide redundancy information indicative of whether the combined address matches any of a plurality of stored addresses;
- a redundancy information latch circuit configured to latch the redundancy information responsive to the oscillating signal and provide the latched redundancy information;
- a second latch circuit configured to latch the first latched refresh address responsive to a number of oscillations of the oscillating signal and provide a second latched refresh address;
- a third latch circuit configured to latch the second latched refresh address responsive to a second active refresh command and provide a third latched address;
- and
- an address predecoder circuit configured to receive the latched redundancy information and the third latched refresh address and perform or skip a refresh operation to the third latched refresh address based on the latched redundancy information.
6 more elements
An apparatus, comprising:
- a memory array including a regular array and a redundant array;
- a row address control circuit configured to refresh memory locations of the memory array responsive to refresh commands, wherein the row address control circuit includes a control circuit configured to latch a first refresh address for first memory locations in the memory array responsive to a first refresh command and prepare for a first refresh operation of the first memory locations, and further configured to latch a second refresh address for second memory locations in the memory array responsive to a second refresh command and prepare for a second refresh operation of the second memory locations, and to perform the first refresh operation responsive to the second refresh command.
An apparatus, comprising:
- a memory array including a regular array and a redundant array;
- a refresh control circuit coupled to the memory array and configured to refresh memory cells of the regular array and the redundant array, wherein the refresh control circuit is configured to produce a plurality of refresh addresses responsive to a first refresh command and to detect whether the plurality of refresh addresses include defective addresses and non-defective addresses, and the refresh control circuit further configured to refresh the non-defective addresses without refreshing the defective addresses responsive to a second refresh command, wherein the refresh control circuit comprises:
- a refresh address counter configured to provide a portion of a refresh address;
- and
- a counter circuit configured to provide a plurality of counts that are each combined with the portion of the refresh address to produce the plurality of refresh addresses.
2 more elements
Dependencies are inferred from the claim text.