US 10,381,061 B2Granted

One-transistor synapse cell with weight adjustment

AssigneeInternational Business Machines Corporation

InventorsJin Ping Han, Xiao Sun, Teng Yang

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Abstract

Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Claims9

Dependent claims

A memory circuit comprising:

a plurality of word lines;
a plurality of bit lines intersecting said plurality of word lines at a plurality of crosspoints;
a plurality of signal lines;
and
a plurality of memory transistor synapse cells located at said plurality of crosspoints, each of said cells comprising:
a memory transistor having a gate;
a pulse shaping unit coupled to a given one of said signal lines and said gate of said memory transistor;
a logic gate having inputs coupled to a corresponding one of said word lines and a corresponding one of said bit lines, and having an output coupled to said pulse shaping unit;
and
a pass gate arrangement coupled to said memory transistor, said corresponding one of said word lines, said corresponding one of said bit lines, and said output of said logic gate;
wherein said pulse shaping unit, said logic gate, and said pass gate arrangement are
cooperatively configured to apply pulses to said gate of said memory transistor for weight adjustment during an update operation and to interconnect said memory transistor to said corresponding one of said bit lines during an inference operation;
and
wherein:
said logic gate comprises an AND gate;
said memory transistor comprises an n-type field effect transistor having first and second drain-source terminals;
and
said pass gate arrangement comprises:
a first pass gate p-type field effect transistor having a first drain-source terminal coupled to said corresponding one of said word lines, a second drain-source terminal coupled to said first one of said drain-source terminals of said memory transistor, and a first gate coupled to said output of said AND gate;
a pass gate n-type field effect transistor having a first drain-source terminal coupled to ground, a second drain-source terminal coupled to said second drain-source terminal of said first pass gate p-type field effect transistor, and a second gate coupled to said output of said AND gate;
and
a second pass gate p-type field effect transistor having a first drain-source terminal coupled to said second one of said drain-source terminals of said memory transistor, a second drain-source terminal coupled to said corresponding one of said bit lines, and a third gate coupled to said output of said AND gate.

19 more elements

A memory circuit comprising:

a plurality of word lines;
a plurality of bit lines intersecting said plurality of word lines at a plurality of crosspoints;
a plurality of signal lines;
and
a plurality of memory transistor synapse cells located at said plurality of crosspoints, each of said cells comprising:
a memory transistor having a gate;
a pulse shaping unit coupled to a given one of said signal lines and said gate of said memory transistor;
a logic gate having inputs coupled to a corresponding one of said word lines and a corresponding one of said bit lines, and having an output coupled to said pulse shaping unit and
a pass gate arrangement coupled to said memory transistor, said corresponding one of said word lines, said corresponding one of said bit lines, and said output of said logic gate;
wherein said pulse shaping unit, said logic gate, and said pass gate arrangement are
cooperatively configured to apply pulses to said gate of said memory transistor for weight adjustment during an update operation and to interconnect said memory transistor to said corresponding one of said bit lines during an inference operation;
and
wherein:
said logic gate comprises an AND gate;
said memory transistor comprises an n-type field effect transistor having first and second drain-source terminals;
said pass gate arrangement comprises:
a pass gate p-type field effect transistor having a first drain-source terminal coupled to said second drain-source terminal of said memory transistor, a second drain-source terminal coupled to said corresponding one of said bit lines, and a gate coupled to said output of said AND gate;
and
a pass gate n-type field effect transistor having a first drain-source terminal
coupled to said first drain-source terminal of said memory transistor, a second drain-source terminal coupled to said second drain-source terminal of said memory transistor, and a gate coupled to said output of said AND gate;
and
said first drain-source terminal of said pass gate n-type field effect transistor and said first drain-source terminal of said memory transistor are coupled to a corresponding one of said signal lines.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/717,023Filed 27 Sep 2017
Published: US 2019/0096462 A128 Mar 2019
Granted: 13 Aug 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

G11C 11/223
Using ferroelectric elements: using MOS with ferroelectric gate insulating film
G06N 3/0499
Architecture, e.g. interconnection topology: feedforward networks
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
G06N 3/08
Neural networks: learning methods