Address control circuit and semiconductor device including the same

A semiconductor apparatus comprising:

• a memory region including a plurality of memory banks, each of the memory banks being configured to receive a block select signal according to an address latch signal and select a subunit memory block defined by the block select signal;
• a repair control circuit configured to perform a repair operation of selecting a redundant word line in lieu of a normal word line of the memory region when an internal address signal corresponds to an internally stored defect address;
• and
• a command and address (command/address) processing circuit configured to receive and decode a command and an external address signal, generate signals pertaining to a normal operation and the repair operation, and provide the signals to the memory region and the repair control circuit,
• the semiconductor apparatus being configured to generate the block select signal according to the external address signal, and generate the address latch signal using a dummy address signal generated to make a transition at a timing substantially identical with a transition timing of the external address signal.