US 10,381,055 B2 · Flexible DLL (delay locked loop) calibration

Abstract

A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

Claims22

Dependent claims

A memory device for storing data, comprising:

an input/output (I/O) interface circuit to exchange data with an associated host controller;
a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface;
and
a control circuit to selectively enable and disable DLL calibration for the DLL circuit in accordance with a DLL calibration mode configured for the memory device to adjust for lower frequency I/O access and higher frequency I/O access of the I/O interface, wherein when selectively enabled, the DLL calibration to operate at one of different time intervals identified by the DLL calibration mode to calibrate the DLL circuit in accordance with phase updates based on lower or higher frequency access, wherein different time intervals indicate different periods of time between consecutive DLL calibration operations, and when selectively disabled, the DLL calibration to refrain from tracking phase updates.

1 more element

Dependencies are inferred from the claim text.

Flexible DLL (delay locked loop) calibration

Life of this patent

Flexible DLL (delay locked loop) calibration

Life of this patent

Abstract

Claims22