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US 10,381,050 B2Granted
Apparatuses and methods for power efficient driver circuits
AssigneeMicron Technology, Inc.
InventorsTimothy M. Hollis, Dean D. Gans, Larren G. Weber
Life of this patent
Estimating the term…
Abstract
An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.
Claims6
An apparatus comprising:
- first, second and third voltage lines configured to receive first, second and third voltages, respectively;
- a plurality of first transistors, each of the plurality of first transistors being coupled between the first voltage line and an output node and configured to receive an associated one of a plurality of first enable signals;
- a plurality of second transistors, each of the plurality of second transistors being coupled between the second voltage line and the output node and configured to receive an associated one of a plurality of second enable signals;
- a plurality of third transistors, each of the plurality of third transistors being coupled between the third voltage line and the output node and configured to receive an associated one of a plurality of third enable signals;
- and
- a plurality of fourth transistors, each of the plurality of fourth transistors being coupled in series with an associated one of the plurality of first transistors between the first voltage line and the output node and configured to receive an associated one of a plurality of fourth enable signals,
- wherein the plurality of third enable signals are different from the plurality of first enable signals and the plurality of second enable signals, and
- wherein each of the plurality of third enable signals is complementary to an associated one of the plurality of fourth enable signals.
5 more elements
An apparatus comprising:
- first, second and third voltage lines configured to receive first, second and third voltages, respectively;
- a plurality of first transistors, each of the plurality of first transistors being coupled between the first voltage line and an output node and configured to receive an associated one of a plurality of first enable signals;
- a plurality of second transistors, each of the plurality of second transistors being coupled between the second voltage line and the output node and configured to receive an associated one of a plurality of second enable signals;
- and
- a plurality of third transistors, each of the plurality of third transistors being coupled between the third voltage line and the output node and configured to receive an associated one of a plurality of third enable signals,
- a plurality of fourth transistors, each of the plurality of fourth transistors being coupled in series with an associated one of the plurality of first transistors between the first voltage line and the output node and configured to receive an associated one of a plurality of fourth enable signals,
- wherein the plurality of third enable signals are different from the plurality of first enable signals and the plurality of second enable signals,
- wherein each of the plurality of third enable signals is complementary to an associated one of the plurality of fourth enable signals, and
- wherein each of the plurality of first transistors is of a first channel type, each of the plurality of second transistors is of the first channel type, each of the plurality of third transistors is of a second channel type, and each of the plurality of fourth transistors is of the second channel type.
6 more elements
Dependencies are inferred from the claim text.