Macro I/O unit for image processor

A computing system, comprising:

• one or more general purpose processors;
• an external memory;
• a memory controller coupled to the external memory;
• and
• an image processor, comprising:
• one or more internal stencil processors each having a respective two-dimensional shift-register array structure;
• a sheet generator;
• and
• an I/O unit configured to read input image data from the external memory for processing by the image processor and to write output image data from the image processor into the external memory, the I/O unit comprising:
• multiple logical channel units, each logical channel unit comprising:
• addressing circuitry configured to generate addresses corresponding to portions of a line group stored in the external memory, and
• reformatting circuitry configured to generate reformatted versions of data read from the external memory,
• wherein each logical channel unit is configured to form a logical channel between the external memory and a respective line buffer within the image processor,
• wherein each logical channel unit is configured to provide reformatted portions of a respective line group stored in the external memory to a line buffer of the image processor including:
• using the addressing circuitry to generate addresses corresponding to respective portions of the line group stored in the external memory, including generating an address corresponding to a first full-width area of the line group having a same width as the line group and repeatedly generating addresses corresponding respectively to a plurality of subsequent areas of the line group, each subsequent area of the plurality of subsequent areas having a smaller width than the line group,
• using the reformatting circuitry to generate reformatted image data comprising reformatted versions of each portion of the respective line group in multiple different respective color formats, and
• providing the reformatted image data to the line buffer,
• wherein the sheet generator of the image processor is configured to load, from the line buffer, multiple sheets having different respective reformatted versions of each subsequent area of the line group into different respective spaces of a two-dimensional shift-register array structure of an internal stencil processor of the one or more internal stencil processors.

A method performed by an image processor comprising one or more internal stencil processors each having a respective two-dimensional shift-register array structure, the method comprising:

• forming, by a logical channel unit of a plurality of logical channel units of an I/O unit of the image processor, a logical channel between an external memory and a line buffer within the image processor;
• using, by the logical channel unit, addressing circuitry to generate addresses corresponding to respective portions of a line group stored in the external memory, including generating an address corresponding to a first full-width area of the line group having a same width as the line group and generating addresses corresponding respectively to a plurality of subsequent areas of the line group, each subsequent area of the plurality of subsequent areas having a smaller width than the line group;
• using reformatting circuitry of the logical channel unit to generate reformatted image data comprising reformatted versions of each portion of the line group in multiple different respective color formats;
• providing the reformatted image data to the line buffer;
• and
• loading, from the line buffer by a sheet generator of the image processor, multiple sheets having different respective reformatted versions of each subsequent area of the line group into different respective spaces of a two-dimensional shift-register array structure of an internal stencil processor of the one or more internal stencil processors.