Shift register unit and driving method therefor

A shift register unit, comprising:

• an input circuit coupled to a first input end, a pull-up node and a second input end, and configured to be controlled by a first input signal receiving from the first input end and a second input signal receiving from the second input end to control a potential level at the pull-up node;
• a pull-up circuit coupled to the pull-up node, a clock signal end and an output end, and configured to be controlled by a clock signal receiving from the clock signal end and the potential level at the pull-up node to generate an output signal to the output end;
• N pull-down circuits each of which coupled to one of N control signal ends, an ith pull-down circuit of the N pull-down circuits coupled to an ith control signal end of N control signal ends, the pull-up node and the output end, and the ith pull-down circuit is configured to be controlled by an ith clock control signal receiving from the ith control signal end to pull down the potential level at the pull-up node and a potential level at the output end, N being a positive integer, i being a positive integer smaller than or equal to N, and
• wherein the N control signal ends receives N clock control signals sequentially from a 1st clock control signal to a N-th clock control signal respectively, the N clock control signals sequentially from a 1st clock control signal to a N-th clock control signal are provided a time delay between any pair of subsequent clock control signals.

A method for driving a shift register unit, comprising:

• receiving, by an input circuit, a first input with a high first input level of the first input from a first input end of the input circuit;
• receiving, by the input circuit, a first power signal with a high first power signal level of the first power signal from a first power signal end of the input circuit;
• driving a pull-up level to a high pull-up level at a pull-up node, wherein the pull-up node is connected to the input circuit and a pull-up circuit and is between the input circuit and the pull-up circuit;
• receiving, by the pull-up circuit, a clock signal with a low clock signal of the clock signal from a clock signal end of the pull-up circuit;
• outputting, by the pull-up circuit, an output signal with a low output signal level of the output signal from an output end of the pull-up circuit;
• driving a second pull-down level to a low second pull-down level at a second pull-down node of a second pull-down circuit and receiving a second control signal with a high second control signal level of the second control signal from a second control signal end of the second pull-down circuit;
• and
• obtaining a first pull-down level to a low first pull-down level at a first pull-down node of a first pull-down circuit and receiving a first control signal with a low first control signal level of the first control signal from a first control signal end of the first pull-down circuit, wherein both the first pull-down circuit and the second pull-down circuit are connected to the pull-up node and the output end.