Handling pipeline submissions across many compute units
AssigneeIntel Corporation
InventorsBalaji Vembu, Altug Koker, Joydeep Ray
Life of this patent
Estimating the term…
Abstract
One embodiment provides for a general-purpose graphics processing unit comprising multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads to be executed is maintained on-chip during execution, a scheduler to schedule a warp to the multiple processing elements, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity, and a logic unit including hardware or firmware logic, the logic unit to group active threads from the warp for execution on the multiple processing elements.
Claims20
A general-purpose graphics processing unit comprising:
- multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads to be executed is maintained on-chip during execution;
- a scheduler to schedule a warp to the multiple processing elements, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity;
- and
- a logic unit including hardware or firmware logic, the logic unit to group active threads from the warp for execution on the multiple processing elements.
A method of managing thread execution on a general-purpose graphics processing unit, the method comprising:
- scheduling a warp to multiple processing elements of the general-purpose graphics processing unit, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity;
- and
- grouping active threads from the warp for execution on the multiple processing elements, the multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads executed by the multiple processing elements is maintained on-chip during execution.
A data processing system comprising:
- a memory to store instructions for execution;
- and
- a general-purpose graphics processing unit comprising:
- multiple processing elements having a single instruction, multiple thread architecture, the multiple processing elements enabled to perform hardware multithreading, wherein execution context for threads to be executed is maintained on-chip during execution;
- a scheduler to schedule a warp to the multiple processing elements, wherein the warp is a group of parallel threads, the warp includes multiple sub-warps, and threads within the warp diverge at sub-warp granularity;
- and
- a logic unit including hardware or firmware logic, the logic unit to group active threads from the warp for execution on the multiple processing elements.
Dependencies are inferred from the claim text.