Loading patent…
AssigneeCadence Design Systems, Inc.
InventorsCraig Franklin Deaton, Lars Lundgren
Estimating the term…
The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying one or more assumptions associated with the electronic design that are mutually in conflict. Embodiments may further include grouping the one or more assumptions that are mutually in conflict into a conflicting group of assumptions and iteratively disabling at least one of the conflicting group of assumptions. Embodiments may include generating at least one trace pair depicting a scenario where an assumption from a disabled set holds in a first trace but is violated in a second trace. Embodiments may further include identifying at least one signal associated with the first trace and at least one signal associated with the second trace and comparing the at least one signal associated with the first trace and the at least one signal associated with the second trace.
A computer-implemented method for electronic design verification comprising:
A computer-readable storage medium for electronic design verification, the computer-readable storage medium having stored thereon instructions that when executed by a machine result in one or more operations, the operations comprising:
A system for electronic design verification comprising:
Dependencies are inferred from the claim text.