Analog design tool, cell set, and related methods, systems and equipment

A system for analog circuit design, comprising:

• an electronic display;
• an input device;
• a memory device having a design tool;
• and
• a processor operably coupled with the electronic display, the input device, and the memory device, and configured to:
• generate and store, in the memory device, pre-defined cells including:
• an architectural cell (A_Cell) having a standard number of circuit elements without internal wiring providing functionality;
• a process specific architectural cell (AP_Cell) generated from the A_Cell to have specific process information for the specific manufacturing process;
• schematic cells (S_Cells) that each include schematic and functional descriptions with internal wiring between circuit elements that is manufacturing process agnostic;
• and
• process specific single cells (SP_Cells) generated by merging data from the AP_Cell and S_Cells, the SP_Cells being a standard size for a specific manufacturing process;
• retrieve pre-defined cells having physical layout information for a specific process stored in the memory device responsive to the schematic layout being created by a circuit designer using an analog circuit design tool;
• build the physical layout by connecting the retrieved pre-defined cells according to the schematic layout;
• store the physical layout in the memory device.

A non-transitory computer-readable storage medium having instructions stored therein, that, when executed by a processor are configured to:

• generate and store pre-defined cells in a memory device, the pre-defined cells including:
• an architectural cell (A_Cell) having a standard number of circuit elements without internal wiring providing functionality;
• a process specific architectural cell (AP_Cell) generated from the A_Cell to have specific process information for the specific manufacturing process;
• schematic cells (S_Cells) that each include schematic and functional descriptions with internal wiring between circuit elements that is manufacturing process agnostic;
• and
• specific single cells (SP_Cells) generated by merging data from the AP_Cell and S_Cells, the SP_Cells being a standard size for a specific manufacturing process;
• retrieve pre-defined cells having physical layout information for a specific process stored in the memory device responsive to the schematic layout being created by a circuit designer using an analog circuit design tool;
• build the physical layout by connecting the retrieved pre-defined cells according to the schematic layout;
• store the physical layout in the memory device.