Layout of standard cells for predetermined function in integrated circuits

A method of generating an integrated circuit layout, comprising:

• designating a manufacturing process, the manufacturing process defining a nominal minimum pitch (T) for metal lines;
• defining a set of standard cell layouts, each standard cell layout being configured for preforming a designated function and having a height (H) wherein a quotient of an expression
• [
• H
• T
• ]
• is a non-integer value;
• defining a virtual array of parallel grid lines aligned along a first direction, a spacing between adjacent grid lines of the virtual array of parallel grid lines, measured in a second direction perpendicular to the first direction, is equal to the nominal minimum pitch;
• defining a series of N cell rows across the virtual array of parallel grid lines, each cell row of the N cell rows extending in the first direction;
• accessing a hardware processor for selecting and placing a selected standard cell layout of the set of standard cell layouts on a corresponding one of the N cell rows whereby each input/output port of the selected standard cell layout is aligned with at least one grid line of the virtual array of parallel grid lines crossing the corresponding cell row;
• and
• creating a new data file corresponding to the integrated circuit layout for storing on a non-transitory storage medium.

A method of generating an integrated circuit layout corresponding to a predetermined manufacturing process comprising:

• encoding a non-transitory storage medium with data corresponding to
• a first set of standard cell layouts corresponding to a predetermined manufacturing process and being configured to perform a predetermined function, the predetermined manufacturing process having a nominal minimum pitch (T) of metal lines along a first direction, and
• a second set of standard cell layouts corresponding to the predetermined manufacturing process and being configured to perform a predetermined function,
• wherein each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts has a cell height (H) along the first direction wherein the cell height is a non-integral multiple of the nominal minimum pitch;
• generating the integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts, and the nominal minimum pitch,
• wherein each standard cell layout of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout in the first set of standard cell layouts;
• and
• creating a new data file corresponding to the integrated circuit layout for storing on a non-transitory storage medium.