Power-aware dynamic encoding
AssigneeSynopsys, Inc.
InventorEmil Gizdarski
Life of this patent
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Abstract
Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression, efficient dynamic pattern compaction and a reduction of toggling rate in the decompressed test stimulus.
Claims16
An EDA tool for transforming a circuit design of an integrated circuit to include design-for-test circuitry, comprising:
- a memory;
- and
- a data processor coupled to the memory, the memory containing software code portions which, when executed by the data processor, define the integrated circuit including a plurality of groups of scan chains and the design-for-test circuitry, the design-for-test circuitry including:
- a static test stimulus source of static test stimulus values;
- a dynamic test stimulus source of dynamic test stimulus values;
- a programmable controller generating a plurality of selection control signals, the plurality of selection control signal designating for dynamic testing a first proper, non-null subset of the groups of scan chains in the integrated circuit;
- a decompressor receiving the plurality of selection control signals and generating decompressed test stimuli in dependence upon the static test stimulus values for all of the groups of scan chains not in the first subset of scan chains, and generating the decompressed test stimuli in further dependence upon the dynamic test stimulus values for the groups of scan chains in the first subset of scan chains;
- and
- circuitry loading the decompressed test stimuli into the plurality of groups of scan chains in the integrated circuit.
An EDA tool for transforming a circuit design of an integrated circuit to include design-for-test circuitry, comprising:
- a memory;
- and
- a data processor coupled to the memory, the memory containing software code portions which, when executed by the data processor, define the integrated circuit including a plurality of scan chains and the design-for-test circuitry, the design-for-test circuitry including:
- a first disjoint set of static variables;
- a second disjoint set of dynamic variables;
- a programmable controller generating a plurality of selection control signals, the plurality of selection control signal designating for dynamic testing a first proper, non-null subset of the groups of scan chains in the integrated circuit;
- a decompressor receiving the plurality of selection control signals and generating decompressed test stimuli including generating care bits in dependence upon the first disjoint set of static variables for all of the groups of scan chains not in the first subset of scan chains, and generating care bits in further dependence upon the second disjoint set of dynamic variables for the groups of scan chains in the first subset of scan chains;
- and
- circuitry loading the decompressed test stimuli into the plurality of scan chains in the integrated circuit.
An EDA tool for transforming a circuit design of an integrated circuit, comprising:
- a memory;
- and
- a data processor coupled to the memory, the memory containing software code portions which, when executed by the data processor, define the integrated circuit including a plurality of scan chains and the design-for-test circuitry, the design-for-test circuitry including:
- at least one variable of a first disjoint set of static variables;
- at least one variable of a second disjoint set of dynamic variables;
- a programmable controller generating a plurality of selection control signals, the plurality of selection control signal designating for dynamic testing a first proper, non-null subset of the groups of scan chains in the integrated circuit;
- a decompressor receiving the plurality of selection control signals and generating decompressed test stimuli in dependence upon at least one variable of the first disjoint set of static variables for all of the groups of scan chains not in the first subset of scan chains, and generating the decompressed test stimuli in further dependence upon at least one variable of the second disjoint set of dynamic variables for the groups of scan chains in the first subset of scan chains;
- and
- circuitry loading the decompressed test stimuli into the plurality of scan chains in the integrated circuit.
Dependencies are inferred from the claim text.