Method for waveform based debugging for cover failures from formal verification
AssigneeCadence Design Systems, Inc.
InventorsPradeep Goyal, Mudit Sharma
Life of this patent
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Abstract
The present disclosure relates to a method for waveform based debugging in a formal verification of an integrated circuit. The method may include receiving, using at least one processor, an electronic circuit design and partitioning a cone of influence for a cover property of the electronic circuit design into design logic and property logic. The method may further include applying an X-value to all inputs associated with the cone of influence and performing an X-simulation until a fixed point is reached. The method may also include identifying a non-X node and providing a path of X-diffusion at a property output.
Claims20
A computer-implemented method for waveform based debugging in a formal verification of an integrated circuit comprising:
- receiving, using at least one processor, an electronic circuit design;
- partitioning a cone of influence for a cover property of the electronic circuit design into design logic that is driving the cover property and property logic corresponding to an expression of the cover property;
- applying an X-value to all inputs associated with the cone of influence;
- performing an X-simulation until a fixed point is reached;
- identifying a non-X node;
- and
- providing a path of X-diffusion at a property output.
A computer-readable storage medium having stored thereon instructions, which when executed by a processor result in the following operations:
- receiving, using at least one processor, an electronic circuit design;
- partitioning a cone of influence for a cover property of the electronic circuit design into design logic that is driving the cover property and property logic corresponding to an expression of the cover property;
- applying an X-value to all inputs associated with the cone of influence;
- performing an X-simulation until a fixed point is reached;
- identifying a non-X node;
- and
- providing a path of X-diffusion at a property output.
A computing system for debugging in a formal verification of an integrated circuit comprising:
- at least one processor configured to receive an electronic circuit design and to partition a cone of influence for a cover property of the electronic circuit design into design logic that is driving the cover property and property logic corresponding to an expression of the cover property,
- the at least one processor further configured to apply an X-value to all inputs associated with the cone of influence and to perform an X-simulation until a fixed point is reached,
- the at least one processor further configured to identify a non-X node and to provide a path of X-diffusion at a property output.
Dependencies are inferred from the claim text.