Connecting designs in mixed language environments

A system comprising:

• a memory system configured to store computer-executable instructions;
• and
• a computing system, in response to execution of the computer-executable instructions, is configured to:
• identify portions of a circuit design to interconnect for functional verification;
• select an interconnect generation technique based, at least in part, on characteristics for the portions of the circuit design;
• elaborate the circuit design, which utilizes the selected interconnect generation technique to generate the interconnect having an intermediate hierarchy between the portions of the circuit design;
• perform functional verification operations on the elaborated circuit design, which allows the portions of the elaborated circuit design to communicate via the generated interconnect;
• and
• present results of the functional verification operations, which includes removing the intermediate hierarchy utilized to generate the interconnect during elaboration to show the portions of the circuit design being directly connected by the interconnect.

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• identifying portions of a circuit design to interconnect for functional verification;
• selecting an interconnect generation technique based, at least in part, on characteristics for the portions of the circuit design;
• elaborating the circuit design, which utilizes the selected interconnect generation technique to generate the interconnect having an intermediate hierarchy between the portions of the circuit design;
• performing functional verification operations on the elaborated circuit design, which allows the portions of the elaborated circuit design to communicate via the generated interconnect;
• and
• presenting results of the functional verification operations, which includes removing the intermediate hierarchy utilized to generate the interconnect during elaboration to show the portions of the circuit design being directly connected by the interconnect.