Systems and methods for modifying a balanced clock structure

A device for modifying a balanced clock distribution network within a circuit design, the device comprising:

• a memory configured to store a circuit design file for the circuit design, the circuit design comprising the balanced clock distribution network, the balanced clock distribution network comprising a plurality of buffers and a plurality of sinks;
• and
• one or more processors coupled to the memory and configured for operations to:
• calculate an estimated arrival time for each buffer of the plurality of buffers and for each sink of the plurality of sinks;
• identify one or more early sinks from the plurality of sinks based on the estimated arrival time for each sink of the plurality of sinks;
• identify one or more early tapoff candidate locations for each early sink;
• estimate a corresponding arrival time adjustment for the one or more early tapoff candidate locations for each early sink;
• select a corresponding early tapoff for each early sink based on the corresponding arrival time adjustment(s);
• and
• generate an updated circuit design file by inserting a corresponding early tapoff at the corresponding early tapoff candidate location for each early sink into the balanced clock distribution network, re-routing modified nets of the balanced clock distribution network including nets attached to the corresponding early tapoff location for each early sink, and inserting one or more route paths between the corresponding early tapoff and an associated early tapoff candidate of the plurality of sinks.

A computer-readable storage medium comprising instructions that, when executed by one or more processors of the device, cause the device to perform operations for modifying a clock distribution network within a circuit design, the operations comprising:

• accessing the circuit design, wherein the circuit design comprises an balanced clock tree structure, the balanced clock tree structure comprising a plurality of sinks and a plurality of buffers;
• determining a timing requirement for each sink of the plurality of sinks, wherein at least a first sink of the plurality of sinks is an early sink associated with an early arrival timing requirement;
• identifying a plurality of early tapoff candidate locations associated with the plurality of buffers;
• estimating, for at least the first sink, a corresponding arrival time adjustment associated with each early tapoff candidate location of the plurality of early tapoff candidate locations;
• selecting a first early tapoff location from the plurality of early tapoff candidate locations based on the corresponding arrival time adjustment for the first early tapoff location and the early arrival timing requirement for the first sink;
• and
• generating an updated circuit design file by inserting a connecting path with at least a first tapoff buffer from the first early tapoff location to the first sink into the circuit design and re-routing affected nets.