Static timing analysis in circuit design

A computer program product for improving path delay calculation in static timing analysis (STA) for a circuit design, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method comprising:

• determining, by a processor, a connectivity between a first device and a second device located in a path of the circuit design, wherein a previous path delay of the path in a previous STA exceeds a desired delay specified by a timing requirement, and wherein determining the connectivity between the first device and the second device in the path of the circuit design comprises:
• comparing, by the processor, a time amount that the previous path delay exceeds the desired delay with a predetermined threshold, and
• determining, by the processor, the connectivity of the first device and the second device in response to the time amount being below the predetermined threshold;
• generating, by the processor, a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, the generated delay constraint reduces pessimistic path delay calculations affecting accuracy of the STA;
• calculating, by the processor, a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint;
• and
• performing, by the processor, timing optimization to the path based on the calculated path delay.